A single semiconductor chip may have two or more circuit blocks that are driven by different respective supply voltages, therefore a digital signal is required to shift from one voltage level to another. Level shifting ensures that signals are of the appropriate voltage when travelling between different circuits, or different portions of a single circuit, having different respective supply voltages. A circuit which performs this function is herein referred to as a “level shifter”.
A conventional level shifter circuit 100 is illustrated in FIG. 1. The voltages VA and VB represent a first and a second supply voltages, respectively; the voltages VA, VB are also called voltage domains. The level shifter 100 comprises a differential cell 200 including a first circuit portion comprising a couple of NMOS transistors M1, M2 with respective gate terminals arranged to receive a differential digital logic input signal, VIN and its Boolean negated value; therefore an inverter I3 is inserted between the gates of M1 and M2. The inverter I3 is a common NOT gate in CMOS technology which comprises a PMOS transistor and a NMOS transistor, M3 and M4 respectively, with drain and gate terminals in common. The supply voltage VA is connected to the source of the transistor M3 and provides the supply for the inverter I3, while the source terminal of the transistor M4 is connected to the ground GND.
A second portion of the differential cell 200 comprises two PMOS transistors M5, M6 having the gate terminals cross-coupled to the drain terminals of M1 and M2, respectively. The second supply voltage VB is connected to the source terminals of transistors M5 and M6. A single output signal VOUT is provided at the common node between the drain terminals of transistors M2 and M6.
In operation, when the input signal VIN is high, the NMOS transistor M1 turns on, so to pull down the gate of the PMOS transistor M6, which turns on and forces the output node to the voltage VB. Instead, when the input signal VIN is low, the transistor M2 turns on pulling down the output node to ground GND (VOUT=0 V).
If the voltage VA is supplied, the level shifter circuit 100 works properly: the signal VOUT is always polarized according to the signal VIN and no static power consumption is possible from VB. In other words, there is no direct current path between the supply voltage VB and ground GND. But if the first supply voltage VA becomes a high impedance (practically when the source is externally removed) the gate terminals of the transistors M1 and M2 are not correctly polarized and some leakage currents could partially turn on the transistors M1 or M2. In this case the cross conduction of the transistors M5-M1 and M6-M2 may verify and the signal VOUT becomes indeterminate.
A level shifter having very low power consumption is known from U.S. Pat. No. 6,285,233 (see, FIG. 2), the disclosure of which is incorporated by reference. The level shifter 110 is different from the level shifter 100 in FIG. 1 because it includes an additional circuit portion 3 comprising an inverter 8 formed by a complementary pair of transistors M7 and M9, respectively, having their respective gate terminals connected to the first supply voltage VA. Furthermore a NMOS transistor M8 is used to control the connection of the gate terminal of transistor M6 in the differential cell 200 to ground GND. A common node C of the transistors M7 and M9 is connected to the gate terminal of the transistor M8; the transistor M8 has a source terminal connected to ground GND and the drain terminal connected to the gate terminal of the transistor M6. A series of transistors M10, . . . , Mn is inserted between the source terminal of the transistor M9 and the second supply voltage VB. These transistors are of the PMOS type with a diode configuration, having their respective gate and drain terminals short-circuited.
The circuit portion 3 provides the level shifter 110 with a very low consumption in absence of the primary domain VA. In fact, when the first supply voltage VA is low, the transistor M7 is off and the gate terminal of the transistor M8 (node C) is driven by means of the series of PMOS transistors M10, . . . , Mn and the transistor M9. A current Ipd flowing through the transistors M10, . . . , Mn, M9 and M7 has a value such to bring the voltage on the node C to a value sufficient to charge the gate capacitance of the transistor M8 and switch it on. In this condition, the gate terminal of the transistor M6 is pulled to the ground GND by the transistor M8 so to turn on the transistor M6; this forces the drain terminal B to the value of the second supply voltage VB. The output VOUT of the level shifter 110 is thus low, having taken the output from the node B through an inverter.
However this solution has a modest consumption of static current during the normal activity and it does not prevent a possible cross conduction when the primary voltage is not present.